Technological Field
The disclosed technology relates to a method of digital-to-analog (DAC) converter mismatch calibration in a successive approximation register analog-to-digital converter (SAR ADC). The disclosed technology also relates to a successive approximation register analog-to-digital converter.
Description of the Related Technology
Analog-to-digital converters (ADCs) are commonly known and are used as an interface between the analog front-end and the subsequent digital processing blocks. Modern wireless communication systems usually require low power with a high resolution (i.e., between 12 to 14 bits). To provide a high enough power efficiency SAR ADCs are used, as these are intrinsically power efficient. A downside of the SAR ADCs is that they are limited to only 8 to 12 bits of resolution due to DAC capacitor mismatch and comparator noise.
Recently, a two-stage pipelined SAR ADC has been proposed that could increase the resolution. The two-stage pipelined SAR ADC comprises two independent medium resolution SAR ADCs and an inter-stage residue amplifier. This pipelined structure relaxes the noise requirements on the second stage but imposes low noise and accurate gain conditions on the inter-stage amplifier.
A known issue with two-stage SAR ADCs, and in general with high resolution ADCs, is that they require a calibration to achieve the best performance. Specifically, the DACs in each stage need to be calibrated with respect to one another; the amplifier can have an offset that needs to be calibrated; the comparators in each stage ADC can be offset; and the amplifier can have a gain error that needs to be calibrated. However, in two-stage SAR ADCs, the known calibration processes require the normal operation of the SAR ADC to be stopped. As such, the SAR ADC cannot continuously convert an input signal. Another advantage is that the known calibration processes do not take into account time-varying changes due to environmental effects.